Integrated circuit failures are among the most technically demanding to investigate. The failure site is typically invisible from the outside — buried inside the mold compound, at a junction too small to resolve without scanning electron microscopy. Decapsulation is the process of removing the package encapsulant to expose the die surface, and it is the essential first step in any serious IC failure investigation. At Aremac Labs, we perform both chemical and mechanical decapsulation, followed by SEM and EDX analysis to characterise the failure site precisely.
ESD and EOS — the most misattributed failures in electronics
Electrostatic discharge (ESD) and electrical overstress (EOS) account for a significant share of IC failures in the field, yet they are routinely misattributed to manufacturing defects or misuse. The distinction matters: ESD events are instantaneous and typically leave a characteristic signature at the gate oxide or junction. EOS events are slower, involve sustained overcurrent or overvoltage, and produce different burn patterns and metallisation damage.
Correctly differentiating ESD from EOS — and ruling out latch-up, junction breakdown, or electromigration — requires physical evidence from the die surface. We open the package, find the damage site, image it under SEM, and interpret what the evidence actually shows rather than defaulting to a generic "electrical overstress" conclusion.
STEP 01
Non-destructive pre-analysis
X-ray imaging, optical inspection, and electrical characterisation before any decapsulation. We map the failure electrically and document the package condition so that evidence is preserved and decapsulation is targeted at the right location.
STEP 02
Controlled decapsulation
Chemical decapsulation using fuming nitric or sulfuric acid depending on package type, or mechanical decapsulation for packages where chemical methods risk damaging the evidence. The process is controlled to expose the die cleanly without introducing artefacts.
STEP 03
Die surface inspection
Optical microscopy followed by SEM imaging of the exposed die. We systematically survey bond wires, bond pads, metallisation layers, and active circuit areas to locate the failure site before applying higher magnification and EDX analysis.
STEP 04
Root cause and report
Interpretation of the failure signature against known ESD, EOS, latch-up, and electromigration mechanisms. We deliver a structured report with SEM images, EDX spectra, root cause determination, and specific corrective action recommendations.
What we investigate
ESD damage at gate oxides and junctions, EOS burnout and metallisation damage, latch-up in CMOS devices, bond wire fracture, ball bond and wedge bond failures, die cracking from mechanical or thermal stress, contamination on bond pads, and passivation layer defects. We work with QFP, BGA, QFN, DIP, SOP, and custom packages across silicon, GaAs, and SiC substrates.